There are strong needs for downsizing, weight reduction and functional upgrading in the recent fields of mobile terminal and information/home appliances, which eventually demands functional upgrading of LSI (large-scale integrated circuit). Thus there is an accelerated trend of fabricating circuits using a plurality of different processes on a single wafer, which is known as SOC (system-on-chip).
SOC, however, requires a longer and more complicated process as compared with a single process, and thus has general tendencies of lower yield ratio and longer development period. SOC is also disadvantageous in that the individual circuits cannot be fabricated according to respective optimum processes since all processes are carried out on the wafer basis, which may yield poorer functions ones rather than those obtained in the single process.
In recent years, interest has been growing on SIP (system-in-package). The SIP is to make various (same kind of, or different kinds of) LSI or IC, which are fabricated by the conventional single process and are already inspected as non-defective, into a unit or module which can be handled as a single component (LSI or IC) by combining and re-wiring. SIP can thus readily realize an LSI unit or IC module having a high yield ratio and a diversified functions.
As a representative structure of the SIP, a chip-on-chip structure typified by an LSI unit 1 is shown in FIGS. 1 and 2. FIG. 1 shows a sectional side elevation of the LSI unit 1, and FIG. 2 shows a plan view of the LSI unit 1 as viewed from the top.
The LSI unit 1 comprises an LSI chip 11 having a lateral length of x1 and a longitudinal length of y1, and an LSI chip 12 having a lateral length of x2 and a longitudinal length of y2 (where x1>x2 and y1>y2).
In the LSI unit 1, the LSI chip 12 having bonding pads 15 is placed on the LSI chip 11 having bonding pads 14 so that the individual active surfaces thereof are faced with each other, and the both are electrically connected by placing bumps 13 in between. To bonding pads 16 of the LSI chip 11, wirings 17 used for connecting the LSI unit 1 to any external circuit (not shown) are bonded.
As shown in FIG. 1, the chip-on-chip structure has advantages in that enabling mounting of a plurality of LSI chips, reduction in mounting area through employment of a three-dimensional structure, and shortening of the wiring between the LSI chips through employment of the face-to-face configuration of the active surfaces.